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John O | April 2017

MIT researchers develop process to iron out wrinkles in graphene


A team of researchers at the Massachusetts Institute of Technology (MIT) have developed a method for manufacturing graphene with fewer wrinkles and for ironing out wrinkles that appear and demonstrated that this process allowed electrons to flow uniformly across the graphene sheet, even in sections that previously had wrinkles.

 

mit_graphene_600

Researchers at MIT have found a way to make graphene with fewer wrinkles,
and to iron out the wrinkles that do appear. (MIT)

 

The most common method for creating graphene is chemical vapor deposition (CVD), in which carbon atoms are deposited on copper foil that has to be removed with chemicals to leave only a sheet of carbon atoms.

 

According to an article on the MIT website, “The CVD process can produce relatively large, macroscropic wrinkles in graphene, due to the roughness of the underlying copper itself and the process of pulling the graphene out from the acid. The alignment of carbon atoms is not uniform across the graphene, creating a ‘polycrystalline’ state in which graphene resembles an uneven, patchwork terrain, preventing electrons from flowing at uniform rates.”

 

In 2013, researchers developed a method for creating single-crystalline graphene from a silicon carbide wafer that had step-like wrinkles at the nanometer level. The researchers developed layer-resolved graphene transfer in which they used a thin layer of nickel to peel off the top layer of graphene from the wafer.

 

“In their new paper,” the article continued, “[researchers] discovered that the layer-resolved graphene transfer irons out the steps and tiny wrinkles in silicon carbide-fabricated graphene. Before transferring the layer of graphene onto a silicon wafer, the team oxidized the silicon, creating a layer of silicon dioxide that naturally exhibits electrostatic charges.

 

“When the researchers then deposited the graphene, the silicon dioxide effectively pulled graphene’s carbon atoms down onto the wafer, flattening out its steps and wrinkles.”

 

This process would not work on CVD-fabricated graphene because the wrinkles are much larger. Once the wrinkles were ironed out, the researchers tested electrical conductivity and discovered that electron mobility was twice as fast.

 

While there is work to be done to scale this process for use in electronics, this research provides starting ground for the manufacture of pristine graphene.

 

The research was recently published in Proceedings of the National Academy of Sciences. The abstract read:

 

“Graphene epitaxy on the Si face of a SiC wafer offers monolayer graphene with unique crystal orientation at the wafer-scale. However, due to carrier scattering near vicinal steps and excess bilayer stripes, the size of electrically uniform domains is limited to the width of the terraces extending up to a few microns.

 

“Nevertheless, the origin of carrier scattering at the SiC vicinal steps has not been clarified so far. A layer-resolved graphene transfer (LRGT) technique enables exfoliation of the epitaxial graphene formed on SiC wafers and transfer to flat Si wafers, which prepares crystallographically single-crystalline monolayer graphene.

 

“Because the LRGT flattens the deformed graphene at the terrace edges and permits an access to the graphene formed at the side wall of vicinal steps, components that affect the mobility of graphene formed near the vicinal steps of SiC could be individually investigated. Here, we reveal that the graphene formed at the side walls of step edges is pristine, and scattering near the steps is mainly attributed by the deformation of graphene at step edges of vicinalized SiC while partially from stripes of bilayer graphene.

 

“This study suggests that the two-step LRGT can prepare electrically single-domain graphene at the wafer-scale by removing the major possible sources of electrical degradation.”

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