introduction

with the increase in power density resulting from advancements in semiconductor packaging technologies comes the issue of heat dissipation. heat is generated as a result of electrical energy being converted to thermal energy during circuit activities. the junction temperature of a chip directly affects the performance of the circuits and the reliability of packages.

figure 1: diagram of electrical test method (etm).

it is very important therefore that the junction temperature of each package be known as accurately as possible through direct measurement. it is further important that such measurement be repeatable, and comparable to measurements made on other packages since it constitutes a measure of performance. and lastly, it is important that the technique of measurement be universally applied in the industry in order to achieve meaningful and unbiased comparison of similar packages.

to this end, the joint electron device engineering council (jedec), under the electronic industries association (eia), is creating a thermal measurement standard for ic packages. the council has recently published the first phase of this standard that is expected to achieve the above goals upon completion.

the purpose of this article is to briefly summarize the essence of this standard, and evaluate some of the issues that are yet to be addressed.

jedec standard

the jedec standard is being developed to create a uniform method of characterizing ic packages in order to establish a frame work by which the performances of different packages housing similar devices, or different devices in similar packages, can be compared.

the choice of measurement technique is the electrical measurement method (etm). etms are not new. they involve the use of forward voltage in temperature sensitive devices such as diodes to determine the temperature of the junction. many companies have been using this method in one form or another, with custom setups or standard available equipment, depending on the sophistication of the user and the complexity of the device. data from tests using this technique have been well published. some of them are referenced at the end of this article [1, 2 & 3].

what the jedec standard does differently, however, is to clearly recommend specific environmental conditions, measurement techniques, fixturing, heating power guidelines, and specific wiring and connection configurations for both thermal dice and active devices.

a unique aspect of the standard is that it calls out for specific test board design. this design specifies the geometry and contacts of the board based on the number of pins, pin sizes and package body sizes. this is aimed at standardizing the impact of printed circuit boards on the thermal performance of the package itself.

the standard consists of different documents some of which are still being developed. the approved documents to date include jesd51(overview), jesd51-1(the electrical test method), jesd51-2 (natural convection environment standard) and jesd51-3 (low thermal conductivity test board for leaded surface mount packages). so far, only surface mount boards have been addressed. the jedec jc-15.1 subcommittee which is responsible for developing this standard, is presently working on board specification for through-holes and other packages.

other documents that are yet to be completed and approved include infrared test method, etm implementation, forced convection, heat sink, high conduction thermal test boards, resistive heating thermal test die, active device thermal test die, and thermal modeling. the list may grow in the future to accommodate inputs from the industry and changes in packaging technologies.

industry review

since the approval of the first phase of the standard, reviews have been very positive. most of the major semiconductor companies have either started to use it or are gearing up to comply. there have also been some issues raised by some potential users of the standards. the jedec-jc15 committee plans to address most of them in subsequent developments of the standards, but we can look at a few of them now.

issues raised on standard

the issues discussed herein are from the author's personal experience in designing to the standard and from questions raised by colleagues in the industry:

1. relevance to non-jedec packages

should non-jedec package designers worry about this standard? since the purpose of the standard is primarily to create a framework against which "different packages carrying similar devices, or similar packages carrying different devices" can be compared and evaluated, it is essentially not package-specific. thus, the author suggests that in order to give an industry-wide validation to their test data, non-jedec packages should also be tested to the same standard.

2. non traditional packages

does the standard address complex, advanced packages? the jedec committee intends to cover as many packages as possible in future revisions of the standard. however, for packages that are highly customized and specialized, the test method, wiring configurations, environmental conditions and powering guidelines, can still be applied to comply with the standard. in such cases, the publication of the results must comply with the requirements for data correction and presentation in the standard.

3. ball grid array (bga) test board design

overwhelmingly most of the questions have been on this topic. in their publication: "thermal resistance characterization of the 225 bga" 4, john pursel and tom tarter discuss some of these issues. the standard is very clear on single layer test boards.

however, the committee has not yet addressed the issue of multiple layer printed circuit boards (pcb's). the design of these boards pose special challenges, especially bga test boards. depending on the number of balls and the ball pitch, the pcb can quickly get very complicated. bgas are a special case because the pcb is very critical to the cooling of the package, particularly in plastic bgas because the board is the principal means of removing heat from these packages.

the issue is how to standardize bga test boards. an important use of thermal data is to enable system designers to predict the thermal performance of their systems. since the chip vendor cannot predict the board designs of all possible users, the vendor will like to evaluate the package itself, as independent from the influence of the board as possible. to achieve this, some companies use the absolute minimum number of layers that the design will allow. this is the vendors's perspective for worst case. however, from the users' perspective, the setup should reflect actual operating conditions, especially if this is significantly different from the vendor's test conditions.

lastly, there is cost. trying to reduce the layers to a minimum often involves having to use minimum trace widths and air gaps. in the pcb industry, any trace width less than 6 mils could exponentially increase the cost of fabrication; therefore, even from the vendor's perspective, the choice of design must also reflect the cost of fabrication. the question then is: which perspective should be used in obtaining test results for publication and comparing with similar device/package performances?

the jedec committee might consider the minimum layer approach using standard trace widths and air gaps, and no thermal enhancements such as thermal vias, for the vendors' perspective test (vpt). for a system designer who wants to evaluate his package for operational conditions, this may be unrealistic. to design for a user perspective test (upt) the board must reflect the user's operating specification.

jedec is still working on finalizing this aspect of the standard. in anticipation of some of these issues the standard calls out for a "complete statement of test conditions and environmental conditions" for presentation of thermal data to be complete and meaningful. what jedec may consider as most critical could be that the instrumentation be set up properly, the device under test (dut) be designed to spec, the test be performed exactly as specified, and all non-specified parameters be clearly documented and published with the result such that the test can be repeated by another person.

test methodology

the jedec jc-15. etm (electrical test method) application can be dynamic or static. dynamic mode involves switching from electrical parameter measurement condition to a heating condition during which power is applied to the dut for a specific period of time, and then switching back to the temperature-sensitive electrical parameter measurement. static mode involves heating the package to steady state and then making temperature measurements.

the temperature sensitive electrical parameter usually takes the form of a voltage drop across a forward biased diode designed into the dut which could be a thermal die or an active device. the measurement current for this diode is selected carefully, so that it is large enough to be reliably measured, but low enough not to create significant package heating. this current often ranges from 100µa to 5ma. thermal dice may contain multiple diodes, strategically located to monitor the temperature of different parts of the die. these chips are also specifically designed to provide uniform heating for the purpose of measuring the thermal resistance of the package.

when measuring thermal resistance, total heating over the die surface should be in compliance with standards of the semiconductor equipment manufacturers international (semi)#g46-88 and eia-jedec standards.

thermal measurement involves initial calibration of the thermal dice in a steady, uniform temperature environment such as a liquid bath or a tightly controlled small oven. calibration is done by measuring the electrical parameters of the measurement diode, such as the forward voltage, at a known temperature. measurements of voltages at different temperatures are then made (at least two points) to obtain a proportionality constant, k(δt/δv, the chip calibration factor.) as shown in fig 2.

figure 2 k-factor curve.

the device is then placed in still air within a specific size box (defined in the standard,) or environment of known air velocity and temperature (yet to be defined in the standard). junction temperature in this known environment is determined by measuring the diode forward voltage and using equation (1) to determine the junction temperature first with no power to the device, and then with the device powered up.

the sequence of powering and taking measurement partially depends on the type of test being performed (static or dynamic). thermal resistance (or impedance, for dynamic test) is the ratio of the difference between the junction and a reference temperature, to the power added as shown in equation (2).

the reference temperature could be ambient for θ_j-a, case temperature for θ_j-c or board temperature for θ_j-b. if significant heating of the ambient air occurs as a result of powering up the device, the temperature change should be factored into the equation as outlined in the jedec standard. reference 1 contains more discussions on the etm.

equipment that can automatically perform this test is available in the market. there are also companies that design and supply the jedec thermal test boards and perform the tests.

conclusion

this standard is a very welcome step towards creating uniformity in the characterization of packages. the review of the standard so far confirms this fact. package thermal performance is becoming increasingly significant as chips become faster and packages get denser. all the more reason to establish a universal method of measuring this important aspect of electronic packaging.

the approved documents and information on the others, questions about the standard, details of data collection, integrity and accuracy can be obtained by contacting the electronic industries association (eia), 2500 wilson blvd., arlington, virginia 22201, usa. the jedec jc15 committee also encourages inputs in the form of comments, suggestions, or desire to participate in the shaping of the standard.

frank mcmaye
president, zealtech design
1012 morse avenue, suite 5, sunnyvale, ca 94089, usa
tel: +1 408 747 1179 fax: +1 408 747 1178
email: [email protected]

references

1. bernie seigal. elements of device thermal characterization, electronic cooling, vol 1, number 1, june, 1995.
2. h. shaukatullay and michael a. gaynes, experimental determination of the effect of printed circuit card conductivity on the thermal performance of surface mount electronic packages, ieee semitherm proceedings, 1994.
3. darvin edwards, ming hang, bill sterns, thermal enhancement of ic packages, ieee semitherm proceedings, 1994.
4. john w. pursel, tom tarter, thermal resistance characterization of the 225 bga. advanced micro devices.