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last time we talked in general terms about detailed modeling, and discussed conditions under which building a detailed model is appropriate. over the next few months, we will discuss some specific details of modeling common ic packages in detail. we will focus on modeling issues regarding cfd analysis, but many of our conclusions will translate to other types of thermal analysis as well.
recall that a detailed model is a model that attempts to represent or reconstruct the physical geometry of a package to the extent feasible. thus the detailed model will physically always look similar to the actual package geometry.
today, let us talk about modeling the die.
structure of a typical die
the die is an essential element of the package and contains the functionality of the device. packages can be either single-die or multi-die. multi-die packages include the mcm (multi-chip module) and mcp (multi-chip package) styles.
however, over the past year or so, stacked die packages have entered the mainstream, chiefly in memory or consumer applications. in this approach several die are stacked vertically on top of each other in a single package. the dice are separated from each other by thin layers of electrical insulation.
fundamentally, a die is made up of a semiconductor material (typically silicon or gallium arsenide) that has the circuitry etched on only one of its sides, known as the active surface. thus the heat generation in a die is confined to a thin layer located on one side of the die.
the conductivity of silicon or gallium arsenide is high enough to preclude any appreciable temperature gradients along the die area. however, the heat generation may or may not be uniform with respect to the die area, depending on the electrical layout of the device.
in some cases, the non-uniformity is significant enough to create large temperature gradients across the die surface. temperature gradients as high as 15 or 20 c have been reported in cases of strong heat flux non-uniformity.
modeling the die
an acceptable model of the die would involve representing the body of the die by a block or cuboidal element, and localizing the heat source to the active surface. some cfd tools use a planar heat source primitive to accomplish this; in that case the heat emanating from the source should be introduced within the die body, just below the active surface.
if the heat flux is significantly non-uniform, it is essential to break down the heat source into a number of smaller sources representing the localized heat fluxes. this will increase the computational cost of simulation, especially in the case of multi-die packages. however, it is well worth it in cases where this temperature gradient is expected to be high.
the conductivity of the common semiconductor materials varies with temperature. this is especially true for silicon. this should be taken into account in the model. most thermal tools have the capability to build in a mathematical function for temperature-dependent conductivity. many have material libraries for
the junction temperature is nothing but the maximum temperature reached in the body of the die. this will normally happen on the active surface. because of the relatively high conductivity of silicon or gallium arsenide, the die will be relatively isothermal if the heat flux is uniform.
about sarang shidore:
sarang shidore obtained engineering degrees from iit madras (india), texas a & m university (college station), and university of texas (austin). he worked at flomerics inc. in various roles in engineering and product management with a special focus on package-level thermal modeling and analysis, a field in which he has authored several papers and articles.
in addition, he worked for mentor graphics as product marketing manager and for several years as a consultant for various organizations. he is currently a visiting scholar at the lbj school of public affairs at the university of texas focused on energy and climate policy and future strategies.
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