Last time we examined modeling
leadframes in leaded packages. In this first month of the new
year, we will take a look at package substrates.
A substrate is a key constituent
of most area array packages, such as Ball Grid Array (BGA) and
Pin Grid Array (PGA). A substrate is essentially an element of
the package on which the die is mounted, and which routes the
I/O’s from the die to the PCB. This is accomplished through a
number of traces etched in the substrate. These traces are present
in one or more metal layers in the substrate.
Substrates in effect fall under
two major categories: Ceramic and Organic.
Ceramic substrates, present in
Ceramic area array packages, have been traditionally used for
their superior mechanical and electrical characteristics. Specifically,
- Are hermetic (do not allow moisture to seep
- Have a relatively high thermal conductivity
(18 W/mK for the most common ceramic dielectric – Alumina)
- Allow for finer line widths and spaces
- Have a good CTE match with Silicon die.
- Allow a large number of metal layers (20 or
Figure 1: Ceramic substrate
The dielectric portion of a ceramic
substrate is typically made from 94-99% pure Aluminum Oxide, or
Alumina. In rare cases Beryllium Oxide or Aluminum Nitride may
also be used, their chief advantage being a much higher thermal
conductivity (ranging from 200 W/mK upwards). The metal layers
in a ceramic substrate are typically made up of Tungsten or Molybdenum.
The ceramic dielectric slabs
are placed together and fired in a high temperature oven in a
specialized and relatively expensive process.
The substrates of plastic area
array packages (e.g Plastic Ball Grid Array) are organic. Essentially,
they are manufactured using standard PCB technology. For traditional
organic substrates, this means an epoxy-glass resin (typically,
BT resin) that makes up the dielectric and copper for the metal
traces and vias.
Figure 2: Organic substrate
The advantages of organic substrates
- The technology used is nearly identical to
that for PCB manufacture. This reduces cost and allows for volume
production easily as compared to ceramic substrates.
- Organic substrates have a good CTE match with
The disadvantages of organic
- Higher thermal resistance compared to ceramic
substrates. Thus they require thermal enhancements for higher
- Poor CTE mismatch with silicon die. This can
be challenging for flip-chip type interconnections, in which
case an underfill must be used.
On the balance though, organic
substrates are the choice for a majority of area array packages,
unless high reliability and/or high powers are requirements (in
which case ceramic substrates hold the advantage).
As organic substrates are more
challenging from a modeling standpoint than ceramic substrates,
let us look at the structure of these substrates in greater detail.
A traditional organic substrate
is typically a 2-layer or 4-layer. The number of layers refers
to the number of metal layers.
A 2-layer substrate has a signal
trace on the top and another metal layer on the bottom, primarily
composed of metal lands for the 2nd level interconnect
(e.g. solder balls).
Figure 3: A 2-layer organic
Signal vias connect the traces
on the top layer to the corresponding lands on the bottom layer.
In addition, a number of vias are also present below the die whose
function is strictly thermal. These are known as thermal vias,
and are usually grounded. They provide a path for the heat to
flow more directly from the die to the solder balls.
A 4-layer substrate is similar to a 2-layer substrate
except that there are two additional metal layers. These are typically
power and ground planes, and not signal trace layers. Because
the copper coverage for power/ground planes is high (usually >
90%), a 4-layer substrate has a significantly smaller thermal
resistance than a 2-layer substrate.
Figure 4: 4-layer organic substrate
Over the last two or three years a different
type of organic substrate technology has gained prominence, especially
for flip-chip type packages. This is called the built-up substrate
technology (also known as HDI, or High Density Interconnect technology).
A built-up substrate is different from the traditional organic
substrate, as it is manufactured by building it up, one layer
at a time. Vias are not drilled mechanically, but using lasers.
Thus the vias are significantly smaller in diameter (~ 4 mils)
and can also be blind or buried. A built up substrate usually
has a core region that is essentially a traditional substrate
structure, flanked by built-up portions above and below this core
Figure 5: Flip-chip package
with built-up substrate
This month we have tried to understand what constitutes
some of the most common substrate technologies in electronics
packaging. Next month, we will examine how to model these various
substrates from a thermal standpoint.
obtained engineering degrees from IIT Madras (India), Texas A
& M University (College Station), and University of Texas (Austin).
Since 1995 he has worked at Flomerics Inc. in various roles in
engineering and product management with a special focus on package-level
thermal modeling and analysis, a field in which he has authored
several papers and articles. Sarang is currently Director of the
Web Business Division at Flomerics Inc. at their Austin office.
He welcomes comments and questions at email@example.com.