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the advent of vertical chip integration, in recent years, has allowed 3d chips to overcome issues such as delay, bandwidth limitation and power consumption in interconnects, which occurs in traditional integrated circuits. by stacking the chips, the footprint of an ic has been drastically reduced; also, the length of the interconnecting wires has been considerably shortened by using vertical vias.

from the thermal perspective, 3d stacked chips pose different challenges than what has been experienced in 2d packaging. for example, the heat dissipation of 3d ics is highly non-uniform and multidirectional, due to the intrinsic chip architecture and the available real estate. when cooling at sub-ambient temperatures is necessary, as may be the case for future applications, the small footprint of a 3d chip becomes an impediment to deploying a cooling solution.

additionally, precision temperature control becomes difficult, since the surface to be controlled may be buried deep in the 3d stack. in response to cooling concerns about 3d ics, this article presents a review of methods available for cooling 3d ics to sub ambient temperatures using tecs. 

click here to read the free, full article, in pdf.