ANSYS announced TSMC certified ANSYS solutions for the seven-nanometer FinFET Plus (N7+) process node with extreme ultraviolet lithography (EUV) technology and validated the reference flow for the latest Integrated Fan-Out with Memory on Substrate (InFO_MS) advanced packaging technology.
The certifications and validations are vital for fabless semiconductor companies that require their simulation tools to pass rigorous testing and validation for new process nodes and packaging technologies.
ANSYS® RedHawk™ and ANSYS® Totem™ are certified for TSMC N7+ process technology that provides EUV-enabled features. Certification for N7+ includes extraction, power integrity and reliability, signal electromigration (EM) and thermal reliability analysis.
Industry-leading TSMC InFO advanced packaging technology is extended to integrate memory subsystem with logic die. TSMC and ANSYS enhanced the existing InFO design flow to support the new InFO_MS packaging technology, and validated the reference flow using ANSYS SIwave-CPA, ANSYS® RedHawk-CPA™, ANSYS® RedHawk-CTA™, ANSYS® CMA™ and ANSYS® CSM™ with the corresponding chip models.
The InFO_MS reference flow includes die and package co-simulation and co-analysis for extraction, power and signal integrity analysis, power and signal electromigration analysis and thermal analysis.
"TSMC and ANSYS' latest N7+ certification and InFO_MS enablement empowers customers to address growing performance, reliability and power demands for their next generation of chips and packages," said Suk Lee, Senior Director of Design Infrastructure Marketing Division at TSMC.
"The number of smart, connected electronic devices continues to grow and manufacturers must keep pace to design power efficient, high-performing and reliable products at a lower cost and with a smaller footprint," said John Lee, General Manager at ANSYS.
"ANSYS semiconductor solutions address complex multi-physics challenges such as power, thermal, reliability and impact of process variation on product performance. ANSYS' comprehensive Chip Package System solutions for chip aware system and system aware chip signoff help mutual customers accelerate design convergence with greater confidence."