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John O | June 2017

IBM announces the development of transistors for 5 nanometer chips


at the 2017 symposia on vlsi technology and circuits that took place in kyoto, japan in early june, ibm announced that it had partnered with globalfoundries and samsung to build a new type of transistor for chips at the five-nanometer node.

 



ibm's nicolas loubet, looking fairly awestruck by a wafer of the new 5nm chips.
(connie zhou/ibm)

 

according to the ibm think blog, “we stacked layers of silicon nanosheets together, horizontally, in order for this new architecture to enable our 5nm transistor to deliver the power and performance boost future applications will demand. the change from today’s vertical architecture to horizontal layers of silicon opened a fourth ‘gate’ on the transistor that enabled electrical signals to pass through and between other transistors on a chip. at these dimensions, it means that those signals are passing through a switch that’s no larger than the width of two to three dna strands, side-by-side.”

 

ibm claims that the five-nanometer transistors enable performance that is 40 percent greater than the 10-nanometer chips at the same power level or 75 percent greater power savings at the same performance level. the blog post admitted that this development is most likely 10-15 years away from market and that the current finfet transistors will remain the standard in the meantime.

 

“the industry has long understood the limits of the various chip architectures,” the blog continued. “our alliance working at the suny polytechnic institute colleges of nanoscale science and engineering’s nanotech complex in albany, ny has known that, for example, it’s possible to build a 5nm finfet transistor from a structural perspective. but scaling from our 7nm chip’s 20 billion finfet transistors per chip, to 30 billion 5nm finfet transistors would not deliver the significant power and performance boost mentioned above.

 

“after about a decade of studying the idea of putting gates all around the transistor – often referred to as gate-all-around (gaa) – stacked nanosheets delivered a gaa transistor for the 5nm node that actually improved density, performance, and power – all built with industry manufacturable tools and processes.”

 

an article from arstechnica explained, “in the case of ibm's gaafet, there are actually three nanosheets stacked on top of each other running between the source and drain, with the gate (the bit that turns the channel on and off) filling in all the gaps. as a result, there's a relatively large volume of gate and channel material—which is what makes the gaafet reliable, high-performance, and better suited for scaling down even further.”

 

it also noted that ibm is using extreme ultraviolet (euv) lithography on the front-end-of-line patterning for its gaafets, which reduces the number of patterning stages on the layer of the chip because of its much narrower wavelength than current lithography machines.

 

learn more about ibm’s development in the video below:

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