to be presented at coolingzone's business & technology summit 2010

cooling challenges of 3d packaging

dr. dereje agonafer

university of texas at arlington

the convergence of computing and communications dictates building up rather than out. as consumers demand more functions in their hand-held devices, the need for more memory in a limited space is increasing, and integrating various functions into the same package is becoming more crucial. over the past few years, die stacking has emerged as a powerful tool for satisfying these challenging integrated circuit packaging requirements. in this presentation, thermo/mechanical challenges in stacked packaging is discussed based on recently published papers. package architectures evaluated in this presentation are rotated stack, staggered stack, stacking with spacers, stacks with thermal vias and package on package. moving forward in more complex combinations such as stacking logic and memory, there is a desire to include thermal design in the upstream phase concurrently with the architecture design. in order to develop design guidelines for microprocessors based on both thermal and device clock performance, it is necessary to know the characteristics of each functional block on the die, guidelines of which are provided by the architectural team. for better thermal performance, the functional blocks are then repositioned and the resulting maximum temperatures are noted for all the cases. recent studies at an attempt to a co-architectural design where design optimization is based on both thermal and architectural objectives will also be addressed.

for more information on the 10th international business & technology summit click here