Special Guest Lecture: Thermal Management for Microprocessors
. by Medhi Asheghi,
"Thermal Engineering Challenges at the Device and Microprocessor Level" and "Near Junction Thermal Engineering of Nanostructured TIM"
The power distribution non-uniformities across chips results in sharp temperature gradients and multiple temperature peaks across a microprocessor or chip, which can adversely impact reliability and performance. Therefore, microprocessor packaging and cooling solutions should not only consider the worst case senario but must also take into account the imapct and ramifiactions of the non-uniformities in power and temperature distributions. Device and package levels thermal design and modeling cover length- and timescales that span over many many orders of magnitude. Often time, the corrolation and connection between the thermal design at the device and package levels are poorly understood. The thermal cooling solutions not only impact the average chip temperature but also impact the peak temperatures and the extent of the heat spreading.
This presentation implements the Spatial Frequency Domain (SFD) analyses of heat transfer in microprocessors to establish a clear relationship between the device and packaging levels thermal design and modeling. I also report on recent advances in the thermal interface material and microprocessor cooling technologies.