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December 2005
library  >  Case Studies  >  Harvard Thermal

Thermal Characterization of Gellium Arsenide FETs


authors: 
kenneth decker, triquint semiconductor
sukyung ko and david rosato, harvard thermal, inc.


abstract


wireless systems such as cell and portable phones, networking and advanced radar systems rely on the performance of high power rf amplifiers. putting out more power at higher frequencies is driving devices to power densities greater than ever. to ensure good reliability of these devices, their operating temperature must be characterized.

 

a comparative investigation between computer based thermal analysis and infrared (ir) microscope testing of triquint's tga9083 gallium arsenide fets is presented. the result will show that a thermal analysis can accurately predict fets' maximum operating temperature.


 

1. background

 

the tga9083 is a phemt power amplifier which operates from 6.5 to 11.5 ghz and is capable of providing 8-watts of rf output power with 35% pae when biased at 9 volts. small signal gain is 19-db. it was chosen for thermal analysis because it is representative of gaas power phemt amplifiers now being built.

 

2. introduction

 

understanding and determining the thermal performance of gallium arsenide (gaas) fets is important to assure reliable operation and electrical performance. today's thermal measurement techniques cannot accurately determine the peak temperatures due to the small geometry. computer thermal modeling provides an important means of determining these hot spots. due to the complex geometry, it is important that these computer models be validated. this paper summarizes the thermal modeling performed on triquint's tga9083 gaas fet circuit and compares the results with infrared (ir) microscope data.

 

3. infrared (ir) testing

3.1 test setup

the following is a description of the thermal infrared measurements of the tga9083 circuit. the tga9083 gaas die was attached to a cm15 (copper molybdenum) carrier plate with gold/tin (ausn) solder, which was bolted to a brass fixture and to the hot-cold plate. thermal grease was used between the brass fixture and the hot-cold plate to enhance heat transfer. the temperature of the bottom of the brass fixture was measured with a thermocouple.


image002.jpg (19336 bytes)

figure 1a. test setup



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figure 1b. test setup


all required electrical and rf connections were made with bond wires as shown in figure 1b above. the barnes infrascope shown in figure 1a was used to view the infrared image of the input and output stages of the die, as shown in figure 2. the procedure for measuring the infrared image of the chip involves painting the chip black and calibrating for temperature and emissivity. the resolution of the imager using a 5x lens (the lens of choice) has a spatial resolution of 8 to 10m.


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figure 2



image008.gif (2434 bytes)
figure 3a


the measurement configuration is shown in the diagram in figure 3a. a close up is also provided showing the die attach region in figure 3b.


image010.gif (1928 bytes)

figure 3b


the contact resistance of the metal-to-metal interface between the carrier plate and the brass fixture has been empirically determined to be 193°c-mm/w.


3.2 test results

infrared measurements were taken with a brass block temperature of 60(c (t-base). the power dissipation of the input stage (q1) was 2.6 watts and of the output stage (q2) was 11.8 watts. measurements were taken with a cm15 thickness of 0.508mm and 1.016mm. figures 4 and 5 show the ir results for the two cases.


image012.jpg (12575 bytes)

figure 4. temperatures with 0.508mm cm15 carrier plate:
ir image measures 201.7°c.

 

image014.jpg (10372 bytes)
figure 5. temperatures with 1.016mm cm15 carrier plate:
ir image measures 181.36°c.


4. thermal characterization

4.1 thermal model description

a geometric based thermal analysis software1, which utilizes a finite difference solver, was used to perform the computer analysis. to accurately predict the maximum fet temperature, two models were created: a package level model and a chip level model.

the first model is a representation of the overall package which includes the gaas chip, the die attach, the cm15 carrier and the brass fixture (thermal spreader) as shown in figure 6. the analysis was performed for two carrier thicknesses: 0.508 mm and 1.016 mm. the second model is a detailed representation of the gaas chip. the fet analyzed has 80 gates, 142 mm wide with a 0.25mm drain length. figure 7 shows the cross sectional area of the fet used in this study. there is a 0.2mm silicon-nitride conformal coating over the topside of the gate and source-drain channel. the "t" gate cross section is 0.25mm wide at the stem and the cap is 0.5mm tall and 0.6mm wide.

 

a quarter model of the chip has been modeled. symmetry along the x-axis and y-axis of the chip was assumed (see figure 8). figure 9 shows the thermal model for the detailed gaas chip.


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figure 6. package model



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figure 7. fet channel cross sectional area.



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figure 8. gaas chip layout.


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figure 9. detailed gaas chip model.


4.2 thermal analysis discussion

due to significant dimensional differences between the fet and the overall package, a package level model could significantly under estimate the maximum fet temperatures in a gaas chip as it will be shown in the forthcoming section. the package dimensions are 4.52 mm x 3.05 mm in comparison to the fet heat source which is 0.25(m x 0.5(m x 142(m. thus, it is necessary to create two models to accurately predict the maximum fets' temperature. the package level model supplied temperatures as boundary conditions for the base of the gaas detailed model. harvard thermal has developed an internal code that three dimensionally maps temperatures from the package level model on to the chip level model.

 

the requirement for the two models is that they must have the same units and orientation, as shown in figure 10. the element size or node locations do not have to be the same between the two models. figure 11 shows a sample temperature contour plot for the package level model and detailed model overlapped after the die attach surface temperatures were transferred into the base of the gaas substrate for the detailed model.

 


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figure 10. alignment of gaas model to the package model.

 


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figure 11. sample temperature contour plot.

 


4.3 thermal analysis assumption

the base of the brass fixture was set to a temperature of 60°c to simulate the test environment described in section 3.0. the thermal conductivity of gaas is highly temperature dependent and in the thermal model followed the relationship: k=56968.5*t-1.23 w/m-(k[2]. orthotropic material properties were used for the ohmic metal (klateral =279.5 w/m-(k, knormal =192.9 w/m-(k)[3], the first metal (klateral =259.8 w/m-(k, knormal =110.2 w/m-(k)[3], and the gate metal (klateral= 252.0 w/m-(k, knormal =90.6 w/m-(k) [3]. all other materials were assumed to be isotropic. the metal-to-metal contact resistance between the brass fixture and the carrier is 193°c-mm/w. the power dissipation is centered 0.1mm below the gate. the heat source is 0.6 mm thick with source to drain length of 0.25mm. the power dissipation per gate is 0.1475 watts.

 

4.4 thermal analysis results

figures 12 and 13 show temperature contour plots for the chip level detailed model using the 0.508mm carrier and the 1.016mm carrier, respectively. the package level models show maximum fet temperatures of 195.7°c and 176.3°c for 0.508mm and 1.016mm carriers, respectively. the detailed level models show maximum fet temperatures of 214.5°c and 194.2°c for 0.508mm and 1.016mm carriers, respectively. these results demonstrate that a package level model can greatly under predict maximum fet temperatures due to the dimensional differences between the package and the fet.


image028.jpg (34441 bytes)
figure 12. detailed level model temperature contour plot for a 0.508mm carrier.


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figure 13. detailed level model temperature contour plot for a 1.016mm carrier.

 


5. comparison of test results vs. analysis results

as seen in figures 12 and 13, there is roughly a 20°c temperature gradient in an 8mm circle around the gate. this is the area over which the infrared data is measured. therefore the peak predicted temperatures cannot be compared to the measured data. to compare the test results and the predicted data, the area weighted average temperatures from the detailed fet models were calculated.



table 1 shows a comparison of temperatures between the ir testing and the thermal analysis:


carrier thickness (mm)

fet temperatures (c)

% difference

ir test

analysis

peak averaged
0.508

201.7

214.5 196.7 3.6
1.016

181.4

194.2 177.2 3.6

 

 

when comparing test results with analysis predictions, one must evaluate possible error of the two. the largest area of error in ir measurements is in calibrating the emissivity of the surfaces being measured. the emissivity may vary between the materials being measured as well as with temperature. the instrument used in this test was calibrated prior to the measurements.

on the analysis side, thermal properties, accuracy of the geometry, accuracy of the analysis tool to solve for temperatures, and power dissipation all impact the predicted results. the accuracy of tool has been proven and the mesh density was tested and shown to be accurate. in this test setup, there is a mechanical interface between the cm15 and the brass block. a contact coefficient of 193°c-mm/w was empirically derived but can vary from test to test. a 20% increase in this coefficient increases the fet channel temperature by 2°c. this alone will reduce the error to 1.8 percent.



6. conclusions

the results of the analysis show a good correlation with the infrared test data. computer simulation of gaas fets pose unique issues. dimensions within a single device can vary by more than three orders of magnitude. with proper modeling techniques and a tool that can simultaneously handle high mesh transitions and temperature dependent and anisotropic thermal properties, accurate fet channel temperature can be predicted. with confidence in the tool and the procedure other devices can be simulated without the need for testing.

 

7. references

1. thermal analysis system (tas) users manual, harvard thermal inc.
2. cindas semiconductor properties report, purdue university, 1988
3. j. wilson and k.d. decker, "gaas mmic thermal modeling for channel temperatures in accelerated life test fixtures and microwave modules," ieee-proceedings, semitherm 10, 1994.

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