last time, we introduced the idea of compact models and also took a look at the history and logic of two-resistor models. we learnt that two-resistor models have the potential of being useful predictors of junction temperature of components in a board-level analysis.

we also reviewed a landmark study that indicated that two-resistor models ought to have a maximum error close to 30% in predicting the junction temperature.

today we will look at some examples of two-resistor models applied to realistic packages, and compare their performance to equivalent detailed models.

two-resistor model topology

recall that a two-resistor model consists of three nodes - junction, "case", and board. the junction node is the die. the board node represents a specified contact point between the package and the board, defined by the jedec junction-to-board resistance standard. the "case" node represents the entire top surface of the package.

the junction-to-board resistance connects the junction and the board nodes, whereas the junction-to-case resistance connects the junction and the "case" nodes.

figure 1: two-resistor model topology

it is important to note that the widely understood meaning of "case" is the point directly above the die center on the top surface of the package (more formally, the surface on which a heatsink can be attached). in the two-resistance model, the "case" node is not representing a point, but rather the entire top surface area of the package.

the implication of what may at first seem a subtle distinction will become clear below.

description of packages

let's take, as an example, two packages - a 352-pin tape ball grid array (tbga) and a more traditional 208-lead plastic quad flat pack (pqfp).

the tbga package is shown in figures 2 and 3 the tbga considered in this study is a 1-metal layer design from toshiba. it has been in high volume mass production for a number of years, predominately supporting asic devices. its main features are shown in figure 2.

the basic construction of the tbga package consists of: gold bumped die, die encapsulant, eutectic (sn 63 % / pb 37 %) solder balls reflow soldered to a single metal layer tape, with a copper cap (nickel plated) attached for mechanical rigidity and heat removal.

the center balls of the package must be depopulated to allow room for the (face down) tab bonded and encapsulated die. tab inner lead bond pitch was 62mm.

figure 2: toshiba 352 tbga

one of the distinctive features of this package is its one-piece, 250mm thick copper cap. the elimination of the traditional stiffener ring in cavity down bgas helps keep its cost down by reducing materials and eliminating an assembly step. the cap must be designed with a raised center portion to accommodate the 350mm die thickness.

from a thermal standpoint, the one-cap design offers equivalent performance to a separate stiffener/coverplate version.

figure 3: 352 tbga package (cross-section)

the pqfp package is a classical leaded package with an epoxy encapsulated die, die flag, bond wires and leadframe. the leads were made of a copper alloy. the package is shown in figure 4.

figure 4: 208 pqfp package

results

experimental data for the tbga was available and used to validate the detailed model, as shown in figure 5. the error in the detailed model was less than 10% in all cases. next a two-resistor model was created according to the jedec standard approaches (described in previous columns).

figure 5: 352 tbga detailed model error

the comparison of the two-resistor model with the detailed model for natural and forced convection is shown in figure 6. it can be seen that the agreement is within 15 % for the junction temperature rise over ambient in all the three cases considered.

figure 6: 352 tbga two-resistor model error
(compared to detailed model)

a similar exercise was repeated for the pqfp. in this case, experimental data was not available, and so the comparison of the detailed and two-resistor models is presented. cases with and without a heatsink were considered for natural and forced convection.

figure 7: two-resistor model error with detailed model
for 208 pqfp

figure 7 shows that the errors for the junction temperature are all within 15%, and that for the case temperature are within 30%.

conclusions

the two-resistor models for both the tbga and the pqfp indicate that the agreement with the detailed models is within the expected bounds for this class of compact models. the errors for the case temperature are in general significantly worse that those for junction temperature.

assuming a uniform heat flux on the die, the silicon die is usually nearly isothermal. hence representing it as a single node in a two-resistor model is consistent with the reality of a single temperature representing the actual die.

the "case" node in the two-resistor model, on the other hand, means in actuality the entire top surface of the package, which is represented by a single node in the network. because the top surface is highly non-isothermal for a plastic package, the two-resistor model is actually reporting some kind of an averaged value of the temperature distribution on this surface.

this translates to a high error when comparing the "case" temperature reported by the model with the temperature of the case point on the detailed model.

about sarang shidore:

sarang shidore obtained engineering degrees from iit madras (india), texas a & m university (college station), and university of texas (austin). he worked at flomerics inc. in various roles in engineering and product management with a special focus on package-level thermal modeling and analysis, a field in which he has authored several papers and articles.

in addition, he worked for mentor graphics as product marketing manager and for several years as a consultant for various organizations. he is currently a visiting scholar at the lbj school of public affairs at the university of texas focused on energy and climate policy and future strategies.