thermal
engineering challenges at the device and microprocessor levels dr. mehdi asheghi mechanical
engineering department
stanford
university to be presented at coolingzone's business & technology summit 2009
the power distribution
non-uniformities across chips results in sharp temperature gradients
and multiple temperature peaks across a microprocessor or chip,
which can adversely impact reliability and performance. therefore,
microprocessor packaging and cooling solutions should not only consider
the worst case senario but must also take into account the imapct
and ramifiactions of the non-uniformities in power and temperature
distributions. device and package levels thermal design and modeling
cover length- and timescales that span over many many orders of
magnitude. often time, the corrolation and connection between the
thermal design at the device and package levels are poorly understood.
the thermal cooling solutions not only impact the average chip temperature
but also impact the peak temperatures and the extent of the heat
spreading.
this presentation implements the spatial frequency domain (sfd)
analyses of heat transfer in microprocessors to establish a clear
relationship between the device and packaging levels thermal design
and modeling. i also report on recent advances in the thermal interface
material and microprocessor cooling technologies. for more information on the 10th international business
& technology summit click here
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