as complexity increases and dies and packages become even larger, temperature gradients also increase, leading to problems with thermal mismatch. hence, thermomechanical analysis grows in importance. apart from the termperature differences, the most important parameter describing thermally induced stress is the coefficient of thermal expansion (cte, or ) expressed in units of microstrain per °c or ppm/°c.

thermally induced stresses manifest themselves at various levels, from junction area to package-level and to interconnection-level. many problems today occur at the interconnection level. for expample, the failure of solder joints forms a large proportion of the total number of fatigue failures in surface-mount components. another common problem is associated with the molding compound/si/leadframe mistmatches.

as the ambient temperature is lowered, stresses increase, because the 'zero' stress condition is the processing temperature which is usually 170°c or higher.

when looking at the available data, it is striking to note the large spread in the published data. this is partly due to variations in the termperature recorded - some authors quote their values at room temperature, others quote the intervale 25 -100°c.

the following table provides data collected from various sources. this edition covers some semiconductor materials, leadframes and solder alloys. the next issue will discuss the temperature dependence of the cte, and current data on the other materials that are of interest to electronic parts: molding compounds, ceramics, board materials, metals and alloys.

recommended literature
1. handbook of electronic package design, ed. m. pecht, 1991, m. dekker, usa, chapters 8 and 12
2. royce, 1988, differential thermal expansion in microelectronic systems, ieee trans chmt-11,
pp. 454-463