future electronics must provide enhanced functionality within a minimal form factor. to address this demand, 3d stacking of ics has emerged as an extremely promising technology able to address the performance requirements of tomorrow’s high speed computing.
this novel technology enables integration of logic, memory, rf and optoelectronic devices on a single chip. the miniaturization comes with the penalty of significant thermal management issues, however. the rate of heat generated per unit volume and thermal resistance increase significantly with each added layer. also, heat removal from the chips placed in the middle of the stack constitutes a major challenge.
this article reviews the design and thermal parametric study of a unique liquid interface thermal management solution for a 3d chip stack.
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